 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| CY7C1340A 128K x 32 Synchronous-Pipelined RAM Features * Fast access times: 5 and 7 ns * Fast clock speed: 100 and 66 MHz * Provides high-performance 3-1-1-1 access rate * Fast OE access times: 5 and 7 ns * Optimal for performance (two-cycle chip deselect, depth expansion without wait state) * Single +3.3V -5% and +10%power supply * Supports +2.5V I/O * 5V tolerant inputs except I/Os * Clamp diodes to VSSQ at all outputs * Common data inputs and outputs * Byte Write Enable and Global Write control * Three chip enables for depth expansion and address pipeline * Address, control, input, and output pipeline registers * Internally self-timed Write Cycle * Burst control pins (interleaved or linear burst sequence) * Automatic power-down for portable applications * High-density, high-speed packages * Low-capacitive bus loading * High 30-pF output drive capability at rated access time Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. The CY7C1340A/GVT71128C32 SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE), depth-expansion Chip Enables (CE2 and CE2), Burst Control Inputs (ADSC, ADSP, and ADV), Write Enables (BW1, BW2, BW3, BW4, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and Burst Mode Control (MODE). The data outputs (Q), enabled by OE, are also asynchronous. Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address Status Controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance Pin (ADV). Address, data inputs, and Write controls are registered on-chip to initiate self-timed Write cycle. Write cycles can be one to four bytes wide as controlled by the Write control inputs. Individual byte Write allows individual byte to be written. BW1 controls DQ1-DQ8. BW2 controls DQ9-DQ16. BW3 controls DQ17-DQ24. BW4 controls DQ25-DQ32. BW1, BW2, BW3, and BW4 can be active only with BWE being LOW. GW being LOW causes all bytes to be written. This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance. The CY7C1340A/GVT71128C32 operates from a +3.3V power supply. All inputs and outputs are TTL-compatible. The device is ideally suited for 486, Pentium(R), 680 x 0, and PowerPCTM systems and for systems that benefit from a wide synchronous data bus. Selection Guide 7C1340A-100 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 5 225 2 7C1340A-66 7 120 2 Unit ns mA mA Cypress Semiconductor Corporation Document #: 38-05153 Rev. *C * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised March 31, 2004 CY7C1340A Functional Block Diagram[1] BYTE 1 WRITE BW1# BWE# CLK D Q BYTE 2 WRITE BW2# D Q GW# BYTE 3 WRITE BW3# D Q BYTE 4 WRITE BW4# D Q byte 4 write byte 3 write Output Buffers byte 2 write byte 1 write DQ1DQ32 CE# CE2 CE2# OE# ZZ Power Down Logic ENABLE D Q D Q ADSP# A16-A2 ADSC# CLR ADV# A1-A0 MODE Binary Counter & Logic Address Register Input Register 128K x 8 x 4 SRAM Array OUTPUT REGISTER D Q Note: 1. The functional block diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information. Document #: 38-05153 Rev. *C Page 2 of 12 CY7C1340A Pin Configuration 100-pin TQFP Top View A6 A7 CE CE2 BW4 BW3 BW2 BW1 CE2 VCC VSS CLK GW BWE OE ADSC ADSP ADV A8 A9 NC DQ17 DQ18 VCCQ VSSQ DQ19 DQ20 DQ21 DQ22 VSSQ VCCQ DQ23 DQ24 NC VCC NC VSS DQ25 DQ26 VCCQ VSSQ DQ27 DQ28 DQ29 DQ30 VSSQ VCCQ DQ31 DQ32 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 CY7C1340A 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC DQ16 DQ15 VCCQ VSSQ DQ14 DQ13 DQ12 DQ11 VSSQ VCCQ DQ10 DQ9 VSS NC VCC ZZ DQ8 DQ7 VCCQ VSSQ DQ6 DQ5 DQ4 DQ3 VSSQ VCCQ DQ2 DQ1 NC Pin Descriptions Name A0-A16 Type InputSynchronous InputSynchronous Description Addresses: These inputs are registered and must meet the set-up and hold times around the rising edge of CLK. The burst counter generates internal addresses associated with A0 and A1, during burst cycle and wait cycle. Byte Write: A byte Write is LOW for a Write cycle and HIGH for a Read cycle. BW1 controls DQ1-DQ8. BW2 controls DQ9-DQ16. BW3 controls DQ17-DQ24. BW4 controls DQ25-DQ32. Data I/O are high-impedance if either of these inputs are LOW, conditioned by BWE being LOW. Write Enable: This active LOW input gates byte Write operations and must meet the set-up and hold times around the rising edge of CLK. Global Write: This active LOW input allows a full 32-bit Write to occur independent of the BWE and BWn lines and must meet the set-up and hold times around the rising edge of CLK. BW1, BW2, BW3, BW4 BWE GW InputSynchronous InputSynchronous Document #: 38-05153 Rev. *C MODE A5 A4 A3 A2 A1 A0 NC NC VSS VCC NC NC A10 A11 A12 A13 A14 A15 A16 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Page 3 of 12 CY7C1340A Pin Descriptions Name CLK Type InputSynchronous InputSynchronous InputSynchronous InputSynchronous Input InputSynchronous InputSynchronous InputSynchronous InputStatic InputAsynchronous Input/ Output Supply Ground I/O Supply I/O Ground Description Clock: This signal registers the addresses, data, chip enables, Write control and burst control inputs on its rising edge. All synchronous inputs must meet set-up and hold times around the clock's rising edge. Chip Enable: This active LOW input is used to enable the device and to gate ADSP. Chip Enable: This active LOW input is used to enable the device. Chip Enable: This active HIGH input is used to enable the device. Output Enable: This active LOW asynchronous input enables the data output drivers. Address Advance: This active LOW input is used to control the internal burst counter. A HIGH on this pin generates wait cycle (no address advance). Address Status Processor: This active LOW input, along with CE being LOW, causes a new external address to be registered and a Read cycle is initiated using the new address. Address Status Controller: This active LOW input causes device to be de-selected or selected along with new external address to be registered. A Read or Write cycle is initiated depending upon Write control inputs. Mode: This input selects the burst sequence. A LOW on this pin selects Linear Burst. A NC or HIGH on this pin selects Interleaved Burst. Snooze: This active HIGH input puts the device in low power consumption standby mode. For normal operation, this input has to be either LOW or NC (No Connect). Data Inputs/Outputs: First Byte is DQ1-DQ8. Second Byte is DQ9-DQ16. Third Byte is DQ17-DQ24. Fourth Byte is DQ25-DQ32. Input data must meet set-up and hold times around the rising edge of CLK. Power Supply: +3.3V -5% to +10%. Pin 14 does not have to be connected directly to VCC as long as it is greater than VIH. Ground: GND Output Buffer Supply: +3.3V -5% to +10%. For 2.5V I/O: 2.375V to VCC. Output Buffer Ground: GND No Connect: These signals are not internally connected. CE CE2 CE2 OE ADV ADSP ADSC MODE ZZ DQ1- DQ32 VCC VSS VCCQ VSSQ NC Burst Address Table (MODE = NC/VCC) First Address (external) A...A00 A...A01 A...A10 A...A11 Second Address (internal) A...A01 A...A00 A...A11 A...A10 Third Address (internal) A...A10 A...A11 A...A00 A...A01 Fourth Address (internal) A...A11 A...A10 A...A01 A...A00 Burst Address Table (MODE = GND) First Address (external) A...A00 A...A01 A...A10 A...A11 Second Address (internal) A...A01 A...A10 A...A11 A...A00 Third Address (internal) A...A10 A...A11 A...A00 A...A01 Fourth Address (internal) A...A11 A...A00 A...A01 A...A10 Document #: 38-05153 Rev. *C Page 4 of 12 CY7C1340A Truth Table[2, 3, 4, 5, 6, 7, 8] Operation Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Address Used None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current CE H L L L L L L L L L X X H H X H X X H H X H CE2 CE2 ADSP X X H X H L L L L L X X X X X X X X X X X X X L X L X H H H H H X X X X X X X X X X X X X L L H H L L H H H H H X X H X H H X X H X ADSC L X X L L X X L L L H H H H H H H H H H H H ADV X X X X X X X X X X L L L L L L H H H H H H WRITE X X X X X X X L H H H H H H L L H H H H L L OE X X X X X L H X L H L H L H X X L H L H X X CLK L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ High-Z High-Z High-Z High-Z High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D Partial Truth Table for Read/Write FUNCTION Read Read Write one byte Write all bytes Write all bytes GW H H H H L BWE H L L L X BW1 X H L L X BW2 X H H L X BW3 X H H L X BW4 X H H L X Notes: 2. X means "Don't Care." H means logic HIGH. L means logic LOW. Write = L means [BWE + BW1*BW2*BW3*BW4]*GW equals LOW. Write = H means [BWE + BW1*BW2*BW3*BW4]*GW equals HIGH. 3. BW1 enables Write to DQ1-DQ8. BW2 enables Write to DQ9-DQ16. BW3 enables Write to DQ17-DQ24. BW4 enables Write to DQ25-DQ32. 4. All inputs except OE must meet set-up and hold times around the rising edge (LOW-HIGH) of CLK. 5. Suspending burst generates Wait cycle. 6. For a Write operation following a Read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH throughout the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP LOW along with chip being selected always initiates a Read cycle at the L-H edge of CLK. A Write cycle can be performed by setting Write LOW for the CLK L-H edge of the subsequent wait cycle. Refer to Write timing diagram for clarification. Document #: 38-05153 Rev. *C Page 5 of 12 CY7C1340A Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Voltage on VCC Supply Relative to VSS ......... -0.5V to +4.6V VIN ...........................................................-0.5V to VCC+0.5V Storage Temperature (plastic) .................... -55C to +150C Junction Temperature ............................................... +150C Range Commercial Industrial Power Dissipation.......................................................... 1.0W Short Circuit Output Current ........................................ 50 mA Operating Range Ambient Temperature[9] 0C to +70C -40C to +85C VDD[10,11] 3.3V -5%/+10% Electrical Characteristics Over the Operating Range Parameter VIHD VIH VIl ILI ILO VOH VOL VCC VCCQ VCCQ Parameter ICC ISB2 ISB3 ISB4 Input LOW (Logic 0) Voltage[12, 13] Input Leakage Current[14] Output Leakage Current Output HIGH Voltage[12, 15] Output LOW Voltage[12, 15] Supply Voltage[12] I/O Supply Voltage (3.3V I/O)[12] I/O Supply Voltage (2.5V I/O)[12] Description Power Supply Current: Operating[16, 17, 18] CMOS Standby[17, 18] TTL Standby[17, 18] Clock Running[17, 18] Conditions Device selected; all inputs < VILor > VIH; cycle time > tKC min.; VCC = Max.; outputs open Device deselected; VCC = Max.; all inputs < VSS + 0.2 or >VCC - 0.2; all inputs static; CLK frequency = 0 Device deselected; all inputs < VIL or > VIH; all inputs static; VCC = Max.; CLK frequency = 0 Device deselected; all inputs < VIL or > VIH; VCC = Max.; CLK cycle time > tKC min. 0V < VIN < VCC Output(s) disabled, 0V < VOUT < VCC IOH = -4.0 mA IOL = 8.0 mA 3.1 3.1 2.375 Typ. 80 0.2 -5 225 2 Description Input HIGH (Logic 1) Voltage [12, 13] Test Conditions Data Inputs (DQxx) All Other Inputs Min. 2.0 2.0 -0.3 -2 -2 2.4 Max. VCCQ + 0.3 4.6 0.8 2 2 0.4 3.6 3.6 VCC -7 120 2 Unit V V V A A V V V V Unit mA mA 8 12 18 30 18 20 mA mA Capacitance[19] Parameter CI CO Description Input Capacitance Input/Output Capacitance (DQ) Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Typ. 3 6 Max. 4 7 Unit pF pF Capacitance Derating[20] Parameter tKQ Description Clock to Output Valid Typ. 0.016 Max. Unit ns/pF Notes: 9. TA is the case temperature. 10. Please refer to waveform (d). 11. Power supply ramp-up should be monotonic. 12. All voltages referenced to VSS (GND). 13. Overshoot: VIH +6.0V for t tKC /2. Undershoot: VIL -2.0V for t tKC /2. 14. MODE pin has an internal pull-up and ZZ pin has an internal pull-down. These two pins exhibit an input leakage current of 30 A. 15. AC I/O curves are available upon request. 16. ICC is given with no output current. ICC increases with greater output loading and faster cycle times. 17. "Device Deselected" means the device is in power-down mode as defined in the truth table. "Device Selected" means the device is active. 18. Typical values are measured at 3.3V, 25C, and 8.5-ns cycle time. 19. This parameter is sampled. 20. Capacitance derating applies to capacitance different from the load capacitance shown in AC Test Loads for 3.3V or 2.5V I/O. Document #: 38-05153 Rev. *C Page 6 of 12 CY7C1340A Thermal Resistance Parameter JA JC Description Test Conditions TQFP Typ. 20 1 Unit C/W C/W Thermal Resistance (Junction to Ambient) Still air, soldered on a 4.25 x 1.125 inch, four-layer PCB Thermal Resistance (Junction to Case) AC Test Loads and Waveforms--3.3V I/O[21] 317 DQ Z0 = 50 50 = 1.5V 30 pF DQ 5 pF 3.3V 3.0V 0V 10% ALL INPUT PULSES 90% 90% 10% 1.5 ns Vddtyp Vddm in tP U = 200us For proper RESE T bring Vdd down to 0V 351 1.5 ns (a) Vt (b) (c) (d) AC Test Loads and Waveforms--2.5V I/O DQ Z0 = 50 2.5V 50 Vt = 1.25V 0V 10% ALL INPUT PULSES 90% 90% 10% 1.8 ns 18 ns (a) (c) Switching Characteristics Over the Operating Range[22] -5 100 MHz Parameter Clock tKC tKH tKL Output Times tKQ tKQX tKQLZ tKQHZ tOEQ tOELZ tOEHZ Set-up Times tS Hold Times tH Address, Controls, and Data In[26] 0.5 0.5 ns Notes: 21. Overshoot: VIH(AC) Description Clock Cycle Time Clock HIGH Time Clock LOW Time Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z[23, 24] Clock to Output in High-Z[23, 24] OE to Output Valid[25] OE to Output in Low-Z[23, 24] Min. 10 4 4 Max. 2 3 0 OE to Output in High-Z[23, 24] Address, Controls, and Data In[26] 2.5 Document #: 38-05153 Rev. *C Page 7 of 12 CY7C1340A Switching Waveforms Read Timing[27] tKC tKL CLK tS tKH ADSP# tH ADSC# tS ADDRESS BW1#, BW2#, BW3#, BW4#, BWE#, GW# CE# ADV# OE# DQ A1 tH A2 tS tS tH tKQ tOEQ tKQ Q(A2) Q(A2+1) Q(A2+2) Q(A2+3) Q(A2) Q(A2+1) tKQLZ tOELZ Q(A1) SINGLE READ Note: 27. CE active in this timing diagram means that all chip enables CE, CE2, and CE2 are active. BURST READ Document #: 38-05153 Rev. *C Page 8 of 12 CY7C1340A Switching Waveforms (continued) Write Timing[27] CLK tS ADSP# tH ADSC# tS ADDRESS BW1#, BW2#, BW3#, BW4#, BWE# GW# CE# A1 tH A2 A3 tS ADV# tH OE# tKQX tOEHZ D(A1) D(A2) D(A2+1) D(A2+1) D(A2+2) D(A2+3) D(A3) D(A3+1) D(A3+2) DQ Q SINGLE WRITE BURST WRITE BURST WRITE Document #: 38-05153 Rev. *C Page 9 of 12 CY7C1340A Switching Waveforms (continued) Read/Write Timing[27] CLK tS ADSP# tH ADSC# tS ADDRESS BW1#, BW2#, BW3#, BW4#, BWE#, GW# CE# A1 A2 tH A3 A4 A5 ADV# OE# DQ Q(A1) Single Reads Q(A2) D(A3) Single Write Q(A4) Q(A4+1) Burst Read Q(A4+2) D(A5) D(A5+1) Burst Write Ordering Information Speed (MHz) 100 66 Ordering Code CY7C1340A-100AC CY7C1340A-66AI Package Name A101 A101 Package Type 100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Operating Range Commercial Industrial Document #: 38-05153 Rev. *C Page 10 of 12 CY7C1340A Package Diagrams 100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-*A Pentium is a registered trademark of Intel Corporation. PowerPC is a trademark of IBM Corporation. All products and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05153 Rev. *C Page 11 of 12 (c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1340A Document History Page Document Title: CY7C1340A 128K x 32 Synchronous-Pipelined RAM Document Number: 38-05153 REV. ** *A *B *C ECN NO. Issue Date 109897 111530 123139 212291 09/22/01 02/06/02 01/19/03 See ECN Orig. of Change SZV GLC RBI VBL Description of Change Changed from Spec number: 38-01003 to 38-05153 Added industrial temp to data sheet Added power up requirements to operating conditions information. Deleted Galvantech info. from title and contents Updated ordering info to match devmaster Deleted 83 MHz (-6) Document #: 38-05153 Rev. *C Page 12 of 12 |
Price & Availability of CY7C1340A-100AC
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |